1. Field of the Invention
The present invention relates to a nonvolatile memory device and memory system incorporating same. More specifically, the present invention is directed to electrically programmable/erasable nonvolatile memory cells and related memory systems.
This non-provisional patent application claims priority under 35 U.S.C §119 to Korean Patent Application 2006-29691 filed on Mar. 31, 2006, the entirety of which is hereby incorporated by reference.
2. Description of Related Art
Due to their ease of use, electrically programmable/erasable nonvolatile memories such as flash memory are rapidly replacing other types of nonvolatile memory, such as erasable programmable read only memories (EPROMs) or mask read only memories (mask ROMs), in the design of many contemporary host devices. For example, flash memory is now commonly used to store programming code.
Indeed, with advances in related semiconductor fabrication technologies, flash memory is increasingly used to provide mass storage capabilities in such devices as digital still cameras and portable audio devices. Current research is focused on providing even greater data storage capabilities for flash memory so that it may be more readily incorporated in video and video recording devices, HDD replacements, etc.
One important technology adapted to improve the data storage capabilities of flash memory is the use of multi-bit memory cells and related programming methods. To store data in conventional flash memory cells, electrical charge is accumulated on or discharged from a floating gate within each memory cell. In a conventional 1-bit flash memory cell, data is stored in relation to two threshold voltage distributions (i.e., two floating gate voltage states equating to digital logic states of “0” and “1”).
However, in flash memory cells adapted to store multi-bit data, at least three and typically four threshold voltage states are defined. For example, in a flash memory cell capable of storing 2 bit data, four threshold voltage distributions for the memory cell are defined to correspond to digital logic states of “00”, “01”, “10”, and “11”, respectively. Using this expanded range of voltage distributions, 2-bit data may be stored on a single memory cell. The digital logic states may be assigned to corresponding voltage distributions as a matter of design choice. However, the use of an increased number of voltage distributions to indicate multi-bit data states necessarily reduces the voltage margins between the various threshold voltage distributions.
Figure (FIG.) 1 shows exemplary threshold voltage distributions (i.e., 1st and 2nd states) for a single-bit (or level) flash memory cell (SLC) in comparison with exemplary voltage distributions (i.e., 1st through 4th states) for a multi-bit memory cell (MLC).
As may be seen from FIG. 1, the threshold voltage distributions for the single-bit flash memory cell enjoy a considerable voltage margin (i.e., separation). This large voltage margin makes discrimination between stored digital logic states relatively easy. On the other hand, the threshold voltage distributions for the multi-bit flash memory cell are respectively separated by much reduced voltage margins.
The processes of accumulating and discharging electrons on and from a floating gate in a multi-bit flash memory cell, (i.e., processes that define a desired voltage distribution), require a delicate balance of applied control voltages in relation to an energy barrier defined by an insulation layer separating the floating gate from an underlying substrate. There are many fabrication and operational variables that influence these processes. For example, if the insulation layer is thinner or thicker than designed, or if applied control voltages are too high or too low, data programming errors may occur. The effects of such variables are exacerbated by the reduced margins between voltage distributions in a multi-bit flash memory cell.
Additionally, charge may leak from a floating gate over time. Leaking charge may eventually result in a changed voltage distribution, and an erroneous data state. Finally, the capability of flash memory cells to securely store charge tends to diminish over time (i.e., after being programmed and read many times).
Many of these data retention and data programming challenges are actually prevalent in single-bit flash memory cells as compared with multi-bit flash memory cells. However, the data transfer speed of most single-bit flash memory is superior to that of the multi-bit flash memory.
FIG. 2 illustrates an exemplary memory cell array for a conventional nonvolatile memory device. The memory cell array is formed from single-bit electrically erasable and programmable memory cells (EEPROM cells), each cell having a floating gate. It will be understood by those skilled in the art that while the memory cell array illustrated in FIG. 2 corresponds to one memory block, multiple memory blocks may be provided in the memory cell array. Storing charge on the floating gate of each EEPROM cell is accomplished by varying the threshold voltage of the EEPROM cell between a low-level value indicating a logic state of “1” and a high-level value indicating a logic state of “0”.
Left in a steady state condition, the floating gate may well retain any stored charge indefinitely. However, since highly energetic charge injection and emission mechanisms are used to repeatedly manipulate the charge state on the floating gate, insulation defects and charge traps are often formed within the insulation layer surrounding the floating gate (e.g., the tunnel oxide). The development of such defects and traps creates reliability problems most commonly manifest during write and erase operations applied to the memory cell. That is, stored electrons may be emitted (i.e., discharge) from the floating gate via defects and traps in the tunnel oxide. Alternately, a floating gate slowly accumulates additional electrons when a control gate has a power supply voltage applied to it during a read operation.
The uncontrolled and undesired loss (leakage) or accumulation of charge on a floating gate inevitably results in an increased or decreased threshold voltage for the EEPROM memory cell. Such threshold voltage deviations result in randomly occurring data bit errors. In view of this result, most contemporary nonvolatile memories include an error correction circuit (ECC) or an error correction control method adapted to detect and/or correct random bit errors.
FIG. 3 is a block diagram of an exemplary nonvolatile memory including an error correction circuit (ECC). The nonvolatile memory includes a memory cell array 300, a write reading circuit (commonly called a “page buffer”) 302, an error correction circuit (ECC) 306, an address decoding and control circuit 308, and a column gating circuit 304. Memory cell array 300 includes electrically rewritable memory cells arranged in a matrix. Page buffer 302 latches write data to be written into memory cell 300, as well as data read from memory cell array 300. ECC 306 generates check data used to detect and correct errors in the page buffer data. Address decoding and control circuit 308 outputs and decodes a control signal for writing data to and reading data from memory cell 300 and controls input/output of data from page buffer 302. Column gating circuit 304 operates in response to address information provided from address decoding and control circuit 308. Memory cell array 300 is configured in memory blocks, each having a series of successively arranged memory cells. The memory cells of the memory blocks are connected to page buffer circuit 302 through a series of bit lines.
FIG. 4 illustrates the operation of a nonvolatile memory including an error correction circuit (ECC) 406. When an externally applied read command is received, the nonvolatile memory performs a read operation. During a read operation, the nonvolatile memory reads data stored at an indicated address in the memory cell array. The read data is detected (or “sensed”) by and stored in a constituent latch circuit within page buffer 402. The sensed and latched read data is then transferred to a column gating circuit 404 associated with ECC 406. ECC 406 seeks within its range of competency to detect and correct error(s) in the read data. During this process, ECC 406 makes use of ECC code (e.g., parity data bit(s)) stored in the memory cell array in association with the actual data. Using this ECC code, ECC 406 may detect and correct data error(s) before outputting the read data to external circuits, such as a host device associated with the memory.
Error(s) in the read data may in many instances be due to degradations resulting from repeated programming and erasure operations applied to the nonvolatile memory device. In terms of general error generation characteristics, the possibility of repeated error generation is very high for a memory block in the memory cell array having previously detected errors. Using conventional approaches such memory blocks are merely treated as “bad blocks” and not used in subsequent read/write operations. Prior to being blocked off from further use, the data in a designated bad block is copy-backed to another memory block.
So-called, “progressive errors” are more commonly generated in nonvolatile memory devices including multi-bit memory cells. Such errors result in reduced reliability of conventional multi-bit nonvolatile memory devices and the designation of many bad blocks. However, the designation of multiple bad blocks leads to reducing overall data storage capacity. Such a reduction in memory capacity cuts against the primary motivation for using multi-bit nonvolatile memory devices in the first place, (i.e., greater data storage capacity achieved through higher data to memory cell integration densities).
Accordingly, there is a requirement for developing memory devices and related memory systems that combine the superior data storage capacity of a multi-bit flash memory cells with the high reliability of a single-bit flash memory cells.